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Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
FEATURES
* High speed differential multiplexer. The device can be configured as a 2:1 multiplexer * Dual 3.3V LVPECL outputs * Selectable differential CLKxx, nCLKxx inputs * CLKxx, nCLKxx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency: 900MHz (typical)
GENERAL DESCRIPTION
The ICS85356I is a dual 2:1 Differential-to-LVPECL Multiplexer and is a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The device has both common select and individual select inputs. When COM_SEL is logic High, the CLKxx input pairs will be passed to the output. When COM_SEL is logic Low, the output is determined by the setting of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1.
ICS
The differential input has a common mode range that can accept most differential input types such as LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The ICS85356I can therefore be used as a differential translator to translate almost any differential input type to LVPECL. It can also be used in ECL mode by setting VCC=0V and VEE to -3.0V to - 3.8V. The ICS85356I adds negligible jitter to the input clock and can operate at high frequencies in excess of 900MHz thus making it ideal for use in demanding applications such as SONET, Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
* Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKxx input * Output skew: 75ps (typical) * Propagation delay: 1.15ns (typical) * LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V * -40C to 85C ambient operating temperature * Lead-Free package available * Compatible with MC100LVEL56
BLOCK DIAGRAM
CLK0A nCLK0A CLK0B nCLK0B SEL0 COM_SEL SEL1 0 1 Q0 nQ0
PIN ASSIGNMENT
CLK0A nCLK0A nc CLK0B nCLK0B CLK1A nCLK1A nc CLK1B nCLK1B 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 SEL0 COM_SEL SEL1 VCC Q1 nQ1 VEE CLK0A nCLK0A nc CLK0B nCLK0B CLK1A nCLK1A nc CLK1B nCLK1B 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 SEL0 COM_SEL SEL1 VCC Q1 nQ1 VEE
ICS85356I
CLK1A nCLK1A CLK1B nCLK1B 0 1 Q1 nQ1
ICS85356I
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm G Package Top View
20-Lead SOIC 7.5mm x 12.8mm x 2.3mm M Package Top View
85356AMI
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
Type Power Input Input Unused Input Input Input Input Input Input Power Output Input Input Input Output Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Description Core supply pin. Non-inver ting differential clock input. Inver ting differential clock input. No connect. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Negative supply pins. Differential output pairs. LVPECL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Common select input. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Differential output pairs. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 14, 20 1 2 3, 8 4 5 6 7 9 10 11 12, 13 15 16 17 18, 19 Name VCC CLK0A nCLK0A nc CLK0B nCLK0B CLK1A nCLK1A CLK1B nCLK1B VEE nQ1, Q1 SEL1 COM_SEL SEL0 nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs COM_SEL 0 0 0 0 1 SEL1 0 0 1 1 X SEL0 0 1 0 1 X Q0 CLK0A CLK0B CLK0A CLK0B CLK0B nQ0 nCLK0A nCLK0B nCLK0A nCLK0B nCLK0B Outputs Q1 CLK1A CLK1A CLK1B CLK1B CLK1B nQ1 nCLK1A nCLK1A nCLK1B nCLK1B nCLK1B
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.6 40 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SEL0, SEL1, COM_SEL SEL0, SEL1, COM_SEL SEL0, SEL1 COM_SEL SEL0, SEL1 COM_SEL VCC = VIN = 3.6V VCC = VIN = 3.6V VCC = 3.6V, VIN = 0V VCC = 3.6V, VIN = 0V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter CLK0A, CLK0B, CLK1A, CLK1B Test Conditions VCC = VIN = 3.6V VCC = VIN = 3.6V VCC = 3.6V, VIN = 0V VCC = 3.6V, VIN = 0V -5 -150 0.15 VEE + 0.5 1.0 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
IIH
IIL VPP VCMR
nCLK0A, nCLK0B, nCLK1A, nCLK1B CLK0A, CLK0B, CLK1A, CLK1B Input Low Current nCLK0A, nCLK0B, nCLK1A, nCLK1B Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1, 2
Input High Current
NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 700MHz 0.6 Typical Maximum VCC - 1.0 VCC - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V0.3V, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 3 Output Rise Time Output Fall Time Duty Cycle Skew 20% to 80% 20% to 80% 200 200 900MHz 0.85 Test Conditions Minimum Typical 900 1.15 75 1.45 150 580 580 100 Maximum Units MHz ns ps ps ps ps
tsk(o)
tR tF todc
All parameters measured at 622MHz unless noted otherwise. This par t does not add measurable jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
V CC
Qx
SCOPE
V CC
LVPECL
VEE
nQx
nCLKxA, nCLKxB V CLKxA, CLKxB VEE
PP
Cross Points
V
CMR
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
nCLKxA, nCLKxB CLKxA, CLKxB nQ0, nQ1 Q0, Q1
tsk(o)
tPD
OUTPUT SKEW
PROPAGATION DELAY
nQ0, nQ1 80% Clock Outputs 80% VSW I N G 20% tR tF
odc = t PW t PERIOD
Q0, Q1
Pulse Width t
PERIOD
20%
OUTPUT RISE/FALL TIME
85356AMI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
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FIGURE 2B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85356I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85356I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 40mA = 144mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.6V, with all outputs switching) = 144mW + 60.4mW = 204.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.204W * 39.7C/W = 93.1C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 6A. Thermal Resistance JA for 20-pin SOIC, Forced Convection
JA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 83.2C/W 65.7C/W 57.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2C/W 39.7C/W 36.8C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance JA for 20-pin TSSOP, Forced Convection
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A OCTOBER 7, 2004
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3. Calculations and Equations.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT RL = 50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 1V)/50] * 1V = 20.0mW Pd_L = [(V - (V - 2V))/R ] * (V
L
OL_MAX
CC_MAX
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER RELIABILITY INFORMATION
TABLE 7A.
JAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0 200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
83.2C/W 46.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85356I is: 446
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
20 LEAD SOIC
PACKAGE OUTLINE - M SUFFIX
FOR
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS - 013, MO - 119
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
Marking Package 20 lead SOIC 20 lead SOIC on Tape and Reel 20 lead TSSOP 20 lead TSSOP on Tape and Reel 20 lead "Lead Free" TSSOP 20 lead "Lead Free" TSSOP on Tape and Reel Count 38 per tube 1000 72 per tube 2500 72 per tube 2500 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85356AMI ICS85356AMIT ICS85356AGI ICS85356AGIT ICS85356AGILF ICS85356AGILFT ICS85356AMI ICS85356AMI ICS85356AGI ICS85356AGI ICS85356AGIL ICS85356AGIL
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85356AMI
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REV. A OCTOBER 7, 2004
Integrated Circuit Systems, Inc.
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
REVISION HISTORY SHEET Description of Change Added Differential Clock Input Interface section. Ordering Information Table - added Lead Free par t number. Updated data sheet format. Date 10/7/04
Rev A
Table
Page 7 13
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